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CMOS XOR/XNOR gate design

Dr. A. yadav


Plot No. 13, Near Manohar Dairy, Zone-1, M.P. Nagar Bhopal, Madhya Pradesh


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This thesis presents a novel thirteen transistor dynamic XOR/XNOR gate intended for advanced microprocessor inbuilt arithmetic and logic unit (ALU). The objectives are to reduce power consumption through dynamic body bias that reduces the threshold of dynamic gate. Traditional dynamic N-Type, dynamic P-Type and dynamic hybrid type is designed and compare with proposed on the basis of following parameter like leakage power, dynamic power, and layout area.

Proposed method utilizes the concept of input body to source bias voltage approach to improve the performance of dynamic XOR//XNOR. It is observed that the new design has lower power dissipation and small layout area. The Monte Carlo simulation of dynamic power consumption also performed to observe the robustness of design against temperature variation.

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Software Requirement :   EDA like Cadence, HSPICE

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